1. Field of the Invention
The present invention relates to an GFIR (Finite-duration Impulse-Response) filter circuit having cascaded bit planes, each of which consists of multipliers and adders, to perform a multiply-add operation.
2. Description of the Background Art
A digital filter is a typical semiconductor integrated circuit intended for use in processing digital signals, such as sound, communication and image signals, and has replaced a conventional analog filter, with developments in digital-signal processing techniques, in the fields of communications and consumer products.
In some cases of digital-signal processing with a digital filter, a digital-signal processing circuit is constituted of filter circuits of different characteristics. An example of this digital-signal processing circuit is shown in a block diagram of FIG. 16. A signal to be processed (input data X) is inputted to filter circuits F1 to FL (L: integer, L.gtoreq.2), and processed therein based on the respective characteristics that the filter circuits F1 to FL have. The processed results are outputted as output data Y.sub.1 to Y.sub.L from the respective filter circuits to a selector. The selector selects a desired one out of the output data Y.sub.1 to Y.sub.L in response to a filter selection signal, and then outputs the desired one as output data y of the digital-signal processing circuit.
Now, a configuration of the filter circuit will be described. In general, a filter circuit consists of several kinds of filters each having a specific filter coefficient C.sub.i (i: integer, i.gtoreq.0). The filter coefficient C.sub.i is constituted of a series of 1-bit coefficient components. In this specification, C.sub.i.sup.j (j: integer, j.gtoreq.0) represents a coefficient component on the (j+1)-th bit from the least significant bit (LSB). For example, the LSB of the filter coefficient C.sub.i is represented as C.sub.i.sup.0 and a coefficient component on the second bit from the LSB is represented as C.sub.i.sup.1. Furthermore, when m is the maximum value of j, the bit length of filter coefficient is (m+1) bit in this representation.
Specifically, a filter circuit consists of cascaded bit planes, each having a combination of multipliers and adders. Coefficient components of a filter coefficient correspond to respective multipliers used in the multipliers included in a bit plane.
A typical example of an FIR filter circuit having cascaded bit planes is shown in a block diagram of FIG. 17. This figure shows a background-art bit plane structure by Tobias G. Noll ("A 40 MHz Programmable Semi-Systolic Transversal Filter" ISSCC Dig. Tech. Papers, pp. 180-191, Feb. 1987). This exemplary filter circuit employs three filter coefficients C.sub.0, C.sub.1 and C.sub.2 each of three-bit coefficient components. According to the above representation C.sub.i.sup.j), the three filter coefficients are represented as C.sub.0 {C.sub.0.sup.2, C.sub.0.sup.1, C.sub.0.sup.0 }, C.sub.1 {C.sub.1.sup.2, C.sub.1.sup.1, C.sub.1.sup.0 } and C.sub.2 {C.sub.2.sup.2, C.sub.2.sup.1, C.sub.2.sup.0 }. Hereafter, a multiplier that multiplies the input data X by the coefficient component is also represented by using the coefficient component.
As can be seen from FIG. 17, this bit plane structure is designed so that the input data X, if processed by multipliers of the same kind of filter coefficient, should be delayed by the same number of delay elements until outputted from the filter circuit, and if processed by multipliers of different kinds of filter coefficients, the input data X processed by a multiplier with coefficient of larger i must be delayed by larger number of delay elements.
For example, the input data X processed by the multiplier C.sub.0.sup.0 are outputted through seven delay elements 2.sub.2, 2.sub.3, 2.sub.4, 2.sub.5, 2.sub.6, 2.sub.7 and 2.sub.8, and similarly the input data X processed by the multiplier C.sub.0.sup.1 are outputted through seven delay elements 1.sub.0, 1.sub.1, 1.sub.2, 2.sub.5, 2.sub.6, 2.sub.7 and 2.sub.8. On the other hand, processed by the multiplier C.sub.1.sup.0, the input data X must be delayed by eight delay elements 2.sub.1, 2.sub.2, 2.sub.3, 2.sub.4, 2.sub.5, 2.sub.6, 2.sub.7 and 2.sub.8, and the number of delay elements that the input data X go through increases by one as compared with when processed by the multiplier C.sub.0.sup.0. Specifically, in the bit plane structure of FIG. 17, the input data X are delayed by seven delay elements when processed by the multiplier C.sub.0.sup.j, eight delay elements when processed by the multiplier C.sub.1.sup.j, and nine delay elements when processed by the multiplier C.sub.2.sup.j until outputted. The above discussion is based on the premise that the delay elements 1.sub.0 to 2.sub.8 should have the same performance.
Now, an operation of the circuit of FIG. 17 will be discussed. In the zeroth bit plane, the input data X to be processed in the filter circuit are inputted to the multipliers C.sub.2.sup.0 to C.sub.0.sup.0 and multiplied by the respective multipliers, to obtain partial products corresponding to the respective multipliers. An adder 10.sub.0 receives the partial product by the multiplier C.sub.2.sup.0 through the delay element 2.sub.0 and the partial product by the multiplier C.sub.1.sup.0. An adder 10.sub.1 receives an output from the adder 10.sub.0 through the delay element 2.sub.1 and the partial product by the multiplier C.sub.0.sup.0, and outputs the addition result as an output of the zeroth bit plane.
The output from the adder 10.sub.1, i.e., the output of the zeroth bit plane is inputted to a multiplier 100.sub.0 not included in any bit plane through the delay element 2.sub.2 also not included in any bit plane. The multiplier 100.sub.0, which has a multiplier 1/2, multiplies the data inputted thereto by 1/2, that is, shifts the data right one bit position and truncates the LSB, and outputs the multiplication result.
On the other hand, the input data X, being delayed by the delay elements 1.sub.0 to 1.sub.2 not included in any bit plane, are inputted to the multipliers C.sub.2.sup.1 to C.sub.0.sup.1 in the first bit plane and multiplied by the respective multipliers to obtain partial products. An adder 10.sub.2 receives the partial product by the multiplier C.sub.2.sup.1 and an output from the multiplier 100.sub.0. An adder 10.sub.3 receives an output from the adder 10.sub.2 through the delay element 2.sub.3 and the partial product by the multiplier C.sub.1.sup.1. An adder 10.sub.4 receives an output from the adder 10.sub.3 through the delay element 2.sub.4 and the partial product by the multiplier C.sub.0.sup.1, and outputs the addition result as an output of the first bit plane.
Similar operation is performed in the second bit plane, and then an adder 10.sub.7 outputs its addition result as the output data Y of the filter circuit.
Furthermore, the background-art bit plane structure of FIG. 17 needs, if the maximum value of i is n, eight ((m+1)(n+1)-1) adders and fifteen ((m+1)(n+1)+m(n+1)) delay elements. The delay elements 1.sub.2, 1.sub.5, 2.sub.2, 2.sub.5 and 2.sub.8 are optionally provided to achieve a desired delay time in accordance with the performance of the delay elements, and may be omitted. Considering that, substantially, only ten ((m+1)n+mn) delay elements are needed.
As shown in FIG. 17, a filter circuit needs many delay elements, adders and multipliers in accordance with the number of kinds of the filter coefficient and the number of coefficient components, thus becoming larger in circuit scale. That increases the area of a chip and boosts the manufacturing cost.
In particular, this disadvantage becomes more pronounced in the digital-signal processing circuit employing a plurality of filter circuits as shown in FIG. 16.